1. Field of the Invention
This invention relates to a semiconductor integrated circuit device in which a semiconductor memory and an operational circuit are integrated.
2. Description of the Background Art
Various operations are carried out on data in a digital signal processing (DSP) application or in a microprocessor. Data to be processed are stored in registers. These data are read from the registers for desired processing.
FIG. 1 is a diagram showing an ordinary digital signal processing system. In FIG. 1, the processing system includes a control circuit 500 for generating various control signals, registers 501 and 502 for writing and reading data under control of the control circuit 500, and an operational unit 503 for carrying out a desired operation on the data stored in these registers 501 and 502.
Where this processing system is a microprocessor, the control circuit 500 decodes a given command and generates various control signals for executing the command. In DSP application, a given signal is decoded to generate control signals necessary for an operation to be carried out between the registers 501 and 502, and the operational unit 503. The control circuit 500, registers 501 and 502 and operational unit 503 are interconnected through a bus 504. Then, the way in which this system works will be described briefly.
It is assumed here that the data are read from the registers 501 and 502 and then processed by the operational unit 503. In this case, the control circuit 500 outputs, through the bus 504, signals (register pointers) for selecting data in the registers 501 and 502 and a control signal for setting the registers 501 and 502 to a read mode. As a result, the selected data are transmitted from the registers 501 and 502 through the bus 504 to the operational unit 503. The operational unit 503 carries out a predetermined operation on the data read-out and outputs a result of the operation to the bus 504. The operation result output to the bus 504 is transferred to another functional block for use therein, stored in a register (501 or 502, or a different register not shown), or output externally.
In such a processing system, a circuit block for carrying out operations on input data is often constructed as one unit where the operations are of a fixed nature.
FIG. 2 is a diagram showing a conventional semiconductor integrated circuit device embodying the digital signal processing system unit described above, which shows schematically a unit for implementing a function to carry out predetermined operations on the data stored in two memories. In FIG. 2, a semiconductor integrated circuit device 600 includes a first memory 100 and a second memory 101. The first memory 100 and second memory 101 are used as registers for storing data to be processed, and correspond to the registers 501 and 502 in FIG. 1.
The first memory 100 includes a memory cell array 100c having a plurality of memory cells for storing data arranged in a matrix of rows and columns, a decoder 100d responsive to a first address ADA for selecting corresponding memory cells in the memory cell array 100c, an input circuit 100a for receiving an input data DIA, generating an internal input data, and writing the data into the memory cells selected by the decoder 100d, and an output circuit 100b for reading a data from the memory cells in the memory cell array 100c selected by the decoder 100d and outputting the data to an exterior of the memory 100. The input data DIA has an n-bit width, and the memory cell array 100c has an m words by n bits structure. The decoder 100d selects one word of n bits. Consequently, the output data DOA output from the output circuit 100b is of n bits also.
The second memory 101 has a construction similar to the first memory 100, and includes a memory cell array 101c having an m-word by n-bit structure, a decoder 101d for decoding a second address ADB and selecting a word (n bits) from the memory cell array 101c, an input circuit 101a for receiving an input data DIB, generating an internal input data, and writing the data into the word (memory cells) in the memory cell array 101c selected by the decoder 101d, and art output circuit 101b for reading a word selected by the decoder 101d from the memory cell array 101c and generating an output data DOB.
Whether the addresses ADA and ADB each include both a row address and a column address or include only a row address is dependent on the structure of the memory cell arrays 100c and 101c. Where a plurality of words are connected in each row in the memory cell arrays 100c and 101c, the addresses ADA and ADB each include both a row address and a column address. Where memory cells corresponding to one word are connected in each row of the memory cell arrays 100c and 101c, the addresses ADA and ADB each include a row address only.
The semiconductor integrated circuit device 600 further includes an operational unit 102 for receiving the output data DOA from the first memory 100 and the output data DOB from the second memory 101, and carrying out a predetermined operation thereon to generate a result data DOS. This operational unit 102 corresponds to the operational unit 503 shown in FIG. 1, and may be an adder, a multiplier or a logic unit. The result data DOS output from the operational unit 102 is of n bits in the illustrated example. The first memory 100 and second memory 101 have the structure of a random access memory (RAM) capable of data writing and reading in random sequence. The way in which this device works will now be described briefly.
The input data DIA and input data DIB are provided from an exterior of the integrated circuit device 600. The input data DIA and DIB may be output data of two sensors supplied through separate routes, or may be two types of data output from different functional units under control of a control block such as the control circuit 500 shown in FIG. 1. A data writing operation will be described first.
The first memory 100 and second memory 101 carry out the same operation as does an ordinary RAM. In the first memory 100, the externally supplied first address ADA causes the decoder 100d to select one word corresponding thereto in the memory cell array 100c. Subsequently, the n-bit input data DIA is converted to internal input data through the input circuit 100a, which is written into the selected n-bit word.
In the second memory 101, as in the first memory 100, the decoder 101d decodes the second address ADB to select one word in the memory cell array 101c. The n-bit input data DIB is written into this selected word through the input circuit 101a.
An operation for reading data from the first and second memories 100 and 101 will be described next. When the first address ADA is supplied, the decoder 100d selects one word (n bits) in the memory cell array 100c. After the one word (n bits) in the memory cell array 100c is selected, the output circuit 100b is enabled, and the n-bit output data DOA is output to an external of the memory 100 through the output circuit 100b.
Similarly, in the second memory 101, the decoder 101d selects one word (n bits) in the memory cell array 101c in response to the second address ADB. Then, the output circuit 101b is enabled to read out data from the selected one word and output the n-bit output data DOB to an external of the memory 100.
The operational unit 102 receives these output data DOA and DOB, carries out the predetermined operation thereon, and outputs the result data DOS (n bits).
By using the semiconductor integrated circuit device described above, operations may be carried out between the group of data A stored in the first memory 100 and the group of data B stored in the second memory 101. If the operational unit 102 is an adder, for example, the following operation may be performed: EQU Ak+Bj=Ci
where Ak and Bj are the k-th and j-th words in the groups of data A and B, respectively, and Ci is the i-th data in a group of output data.
If the operational unit 102 is comprised of a multiplier and an accumulator, with the first memory 100 and second memory 101 storing matrix data A and B, respectively, the following matrix operation may be performed: EQU .SIGMA.Aij.multidot.Bjk=Cik
where Aij is a data word in the i-th row and j-th column of the matrix A, Bjk is a data word in the j-th row and k-th column of the matrix B, and Cik is a data word in the i-th row and k-th column of a resultant product matrix.
In the conventional semiconductor integrated circuit device described above, the first memory, second memory and operational unit must be arranged separately as shown in FIG. 3. FIG. 3 is a diagram schematically showing a layout of the first memory, second memory and operational unit in the integrated circuit device 600.
The case is considered now in which respective circuit blocks, i.e. the first memory 100, second memory 101 and operational unit 102, are arranged separately as shown in FIG. 3. The operational unit 102 receives the two inputs each in n bits. Memory cells corresponding to a plurality of words are usually connected in each row in the first and second memories 100 and 101. Thus, the operational unit 102 has a smaller width than the memories 100 and 101, which gives rise to the problem that regularity cannot be secured for the layout within the integrated circuit device 600.
That is, the sum of the widths (horizontal directional lengths in FIG. 3) of the first memory 100 and second memory 101 is greater than the width of the operational unit 102. Thus, if the operational unit 102 is disposed in a position equidistant from the first memory 100 and second memory 101, empty regions E1 and E2 are present in the semiconductor integrated circuit device 600 as shown in FIG. 3. It means that the semiconductor integrated circuit device 600 has a low efficiency of chip area utilization, causing an obstacle to large scale integration.
Even where each row in the first memory 100 and second memory 101 represents one word, that is to say memory cells of n bits are connected in each row, the sum of the widths of the first memory 100 and second memory 101 is greater than the width of the operational unit 102 since the first memory 100 and second memory 101 require peripheral circuits such as the decoder circuits for selecting memory cells. Consequently, as in the foregoing case, regularity cannot be secured for the layout.
Further, the first memory 100 and second memory 101 are connected to the operational unit 102 through relatively long interconnection lines L1 and L2, respectively. This causes the problem of signal delays due to the lines L1 and L2, resulting in slow processing speed. The lines L1 and L2 have different lengths particularly where another control circuit is disposed in one of the empty region E2 shown in FIG. 3, with the operational unit 102 displaced toward the other empty region E1, in order to improve the layout regularity. In this case, the processing speed of the integrated circuit device is determined by the delay due to the longer interconnection line, hence processing is further retarded.
In DSP application or in a microprocessor, the semiconductor integrated circuit device 600 is integrated on a single chip with other functional blocks (functional units) as shown in FIG. 4. If the semiconductor integrated circuit device lacks in layout regularity as noted above, the functional blocks 650 and 651 and other devices cannot be arranged in high density on the semiconductor chip 700. Thus, it is impossible to realize a high dense large-scale integration circuit device.
Where such a semiconductor integrated circuit device is used in DSP application in particular, the functional blocks 650 and 651 are often formed of gate arrays, and a highly dense and highly integrated gate array logic cannot be realized. Further, if the processing speed of such a large-scale integration circuit device is determined by the operating speed of the semiconductor integrated circuit device 600, the latter being slowed by the delays due to the interconnection lines as noted above, then the processing speed of the large-scale integration circuit formed on this chip 700 must become slow also.